High-speed Placement and Routing
P.R. Editor XR5000 HS
Zuken’s highest level router. Including all of the features and functionality found within Place and Route Editor XR2000, Place and Route Editor XR5000 HS (high-speed) offers specific additional functionality targeted for high-speed PCB design, such as DDR2, DDR3, DDR4 and PCI Express. It obeys a wide range of fast circuit rules including min/max length, skew, delay and crosstalk limits to meet tight timing and noise margins. Manual and automatic editing tools enable nets to be tuned precisely for track length or flight-time to achieve optimum timing characteristics.
Features
Constraint Manager
The integrated Constraint Manager provides a fast and effective way to create and view even the most complex net constraints, using a familiar spreadsheet style interface, by grouping critical nets into logical groups, constrain them by assigning differential pairs, skew groups or ‘family’ skew values to quickly build a constraint hierarchy in just a few clicks of the mouse. Constraint information is stored in a database that is shared with PCB layout, routing, verification and analysis, providing a smooth exchange of data and a consistent user interface across all applications in the design flow.
Topology Editor
To achieve the desired timing requirements for high-speed nets, engineers must consider the proper connectivity and pin order for routing. Topology Editor provides engineers with a schematic view of the complete signal with tools to assign predefined topologies such as daisy chain, H-tree or star, or create custom templates to apply to a range of high-speed nets.
Resources
DownloadDatasheet: CADSTAR Routing Matrix
Overview of the features deliverd with the several P.R. Editor modules available for CADSTAR.
DownloadDatasheet: CADSTAR High-speed Place and Route Editor
Including all of the features and functionality found within Place and Route Editor XR2000, Place and Route Editor XR5000 HS (high-speed) offers specific additional functionality targeted for high-speed PCB design, such as DDR2, DDR3, DDR4 and PCI Express.
Read MorePCB Design: Manual Routing with Broader Brush Strokes
This post is dedicated to the PCB designer who logs hundreds of hours each year manually routing complex PCB designs while wishing the activity was not so detailed and stressful.
Read MoreBGA Packages: Are You Designing Your High-speed Memory Networks in the Dark?
Do you know what’s going on inside of your BGA devices, but do not have sufficient functionality in your ECAD software to address advance timing skews?
Read MoreCreating BGA Fan-outs Manually Can Account for 25-30% of Your PCB Design Time - Let's Automate
Fanning out high pin-count BGAs can be a simple one click operation, and creating escape patterns from the fan-outs can be done automatically as well. How long did you spend on your last PCB design on the BGA components alone?
Read MoreTrunk Routing vs. Bus Routing: They're the Same Thing, Right?
Recently, a discussion flared up in our office after someone questioned the use of the term ‘trunk routing’. They wondered whether it’s really a term in its own right – or just a fancy name for bus routing?
DownloadDatasheet: CADSTAR High-speed Place and Route Editor
Including all of the features and functionality found within Place and Route Editor XR2000, Place and Route Editor XR5000 HS (high-speed) offers specific additional functionality targeted for high-speed PCB design, such as DDR2, DDR3, DDR4 and PCI Express.