Concurrent and Post-layout Signal Integrity


High-speed interfaces such as DDRx and PCI Express demand complex timing requirements that cannot be resolved by applying traditional rules of thumb to secure effective signal quality. CADSTAR SI Verify offers a complete concurrent and post-layout signal integrity solution that enables engineers, layout designers and specialists within a development team to collaborate, organize, constrain, and verify their design in a seamless process. This helps them work more effectively, minimize costs, and improve overall time to market.

CADSTAR Signal Integrity Verify utilizes the Constraint Browser spreadsheet-style interface that also simplifies design navigation and constraint entry for the CADSTAR Place and Route, Signal Integrity Verify and Power Integrity Advance tools.

Features and Benefits
Integrated within CADSTAR High-speed design suite for concurrent and post-layout SI analysis and constraint verification
Accurate transmission line analysis for fast calculation of reflection and crosstalk effects
Embedded simulation model library includes standard IC models and an IBIS 5.0 parser
Support for eye diagrams, frequency domain/S-Parameter simulations, and parameter sweeps
Time domain analysis supports frequency-dependent “skin effect” and Ohmic losses for accurate simulation into the GHz domain
Perform virtual measurements at the IC package pin or directly on the silicon die
Frequency domain simulation supports S-Parameter and transmission line impedance, with the option to export S-Parameter data in Touchstone format
Design Management and Navigation
Design Management and Navigation

CADSTAR SI Verify utilizes the constraint manager spreadsheet-style interface to simplify design management, classification and constraint entry.

From the constraint manager, easily generate simulation results within the SI Simulator (waveform viewer) or directly populate the constraint spreadsheet with simulation and measurement results. The design tree view simplifies management and classification of nets and components within a design, and provides easy access to conduct “what-if” analysis to study and determine best strategies for signal termination and topology.

CADSTAR SI Verify includes a standard library of IC models. You can import or build your own models using IBIS, SPICE sub-circuit, or user-defined transmission line/lumped element models to support accurate analysis of critical signals in your design.

Layer Stack-up
Layer stack-up definition

The layer stack-up can be modeled to determine the characteristic impedance of critical transmission lines, accommodating track profile for both rectangular and trapezoidal mode, enabling either the embedded finite element method (FEM) or boundary element method (BEM) field solver and advanced construction materials to achieve accurate results. Frequency-dependent losses and induced crosstalk for coupled lines are included for enhanced accuracy at higher frequencies.

Interactive and Batch Simulation
Batch simulation

CADSTAR SI Verify works in both time and frequency domain modes to analyze transmission lines parameters and provide fast analysis of reflection and crosstalk, in addition to measuring timing and delay characteristics. You can run interactive or batch simulation for single or coupled lines, returning a range of graphical results including:

  • Voltage over time
  • FFT (Fast Fourier Transformation) to identify frequency-based hot-spots
  • Fast eye diagram generation, with mask to verify compliance to specification
  • Frequency-domain analysis for transmission line impedance and S-Parameter results of the whole interconnect
  • Parameter sweeps for discrete values, trace parameters and driver/receiver models for expanded analysis of high-speed interfaces, such as the optimization of on termination (ODT) settings
  • Easy-to-use interactive and automatic measurement tools to capture critical points, such rise/fall time and over/undershoot
Scenario Editor
Scenario Editor

The graphical Scenario Editor lets you explore alternate design strategies to assess the best approach to meet your design objectives. You can model a virtual prototype using vendor-supplied IBIS models or generic devices from the built-in library, to evaluate different termination styles and net topologies.


Tews Significantly Reduces Development Time and Cost of Complex High-speed PCBs using Concurrent Power Integrity Simulation

TEWS Technologies encountered challenges around power distribution on PCBs for their embedded interface modules, due to today’s increasingly complex designs.

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Datasheet: CADSTAR SI Verify

Complete post-layout signal integrity simulation toolset.

    Signal Integrity
    TEWS Technologies logo
    “We found the Zuken SI Verify and Power Integrity Advance tools quick and easy to use from the outset.”
    – Michael Költzow, Senior CAD Engineer

    Read Success Story