Integrated Environment for Designing PCBs, BGAs and MCMs
Board Designer provides an intuitive, integrated environment for designing PCBs, BGAs and MCMs. It serves to guide the user, via a common user interface, from circuit design through to floorplanning, placement and routing, analysis and into manufacturing. Rules are constant throughout the design process and are dynamically linked to ensure flexibility and consistency.
- A single, intuitive environment with a coherent approach throughout the design process, easy links between tools, and a common database and libraries
- Rules-driven design for correct-by-design outcomes
- An optimized combination of automatic, semi-automatic, and interactive functionality to maximize design productivity
- Design partitioning facilitates intelligent, concurrent engineering; especially useful for large or complex products and for the re-use of proven circuits
- Re-use of proven circuit blocks saves time
- Floor Planning and Routing
- Team-based Design
- Build-up Technology
- Embedded Component Design
- Placement DRC
- Add-on Tools
This tool enables floor planning of individual components and groups of components, taking account of the side of the board on which they are to be placed. This information, together with both component and net information is linked with Design Gateway.
Wiring input is made easier because fillets and tangent arc shapes can be generated simultaneously. Real-time spread is supported for wiring and surface shapes. Online design rule checking (DRC) takes account of resist patterns and ensures equal-potential nets.
Unconnected nets can be automatically detected and selected during interactive routing. Additionally, an automatic bus wiring and editing function identifies those nets that are suitable for bus wiring in advance, simplifying bus input operations. Placement and wiring information can be automatically copied and placed elsewhere in the design. Move components with indicators guiding users for optimum location and dynamically consider the virtual wiring length during placement. Component push and rewiring after placement are also supported.
Components can be grouped together and, by creating a group region, preliminary placement and component DRC checks can be carried out, taking account of wiring blocks.
All data assigned to nets and components are confirmed in real-time using a dialog display. Furthermore, maximum and minimum wiring length limits are displayed in graphical form during wiring and relocation.
Net density is displayed in real-time when wiring after component placement. The degree of detour can be specified in the calculation of virtual net lengths, and this allows checks to be made in conditions where actual wiring is assumed to have been carried out. Additionally, net density is constantly checked while components are moved.
Even when there is no indication of bypass capacitors on the schematic diagram, batch generation can be carried out in the vicinity of the corresponding IC. Batch generation is also available for fillets, shield patterns, surface patterns for reinforcement, and the like. Detailed parameters that specify factors such as the arc radius and connection component can be set. Supplementary vias that are effective in lowering the impedance of power supplies and grounds can be batch generated and a myriad of dimension line patterns can be created for length, diameter, angle, lead, etc. Positions, arrow shapes, and repeat input can also be specified.
Gerber data, HP-GL/HP-GL2 format plotter data, layer data from separate PCB files, and similar information can be read during interactive design.
By defining regions on a PCB and dividing them with connection information intact, multiple designers can work on each region. Furthermore, the consistency of the board’s design information is maintained. Partitioning in copy mode is also supported. Design File Manager presents the partitioned data using a hierarchical display. Monitoring functionality allows designers to view other files currently opened by other engineers. During division, connectors that indicate the connection points for partitioned sections can be generated.
Upon expansion, it is possible to specify a wide range of different options relating to, for example, the integration of surfaces, the preservation of land conditions, and the layers to be expanded.
Build-up technologies that reduce layer count and improve board density are supported through dedicated commands in combination with libraries of layer configurations, vias, and clearance rules. The Build-Up Rule Editor is a dedicated visual editor for setting via and clearance rules for build-up boards. Additionally, a double via checking function enables correct generation of double vias for connection reinforcement or improving current carrying capacity. An optional, web-based service provides a library file of layer configurations, vias, and clearance rules for the build-up board specifications from a variety of board manufacturers.
Using the 3D Viewer/Editor in CR-5000 Board Designer, vias displayed in 3D format can be moved and modified. 3D Viewer function within BD can be used to change the view of any design at any stage into 3D, thus allowing you to look through the design to see inner layers/complex areas – ideal for HDI/dense multi-layer boards.
This module supports designs with components embedded between board layers. This technique not only saves space but can improve electrical performance, both in terms of signal integrity and EMC performance, particularly in high-speed circuits. Placement sides of the PCB and layer positioning can both be specified while moving components and DRC checks take into account copper foil thickness and insulator thickness. Checks can be performed having set placement side restrictions set for each individual inner layer.
Design rule checking (DRC) extends into component placement in CR-5000 Board Designer. Clearances between components, placement sides, and angular restrictions can be checked. In addition, the maximum wiring length set for a net can be checked at the floor planning stage. Check items have been provided to support the ever diversifying specifications of PCBs.
In-depth checking of equal-potential nets, checked in accordance with the PCB specification, and checking wiring lengths, topology, and other factors necessary for high-speed boards are all supported.
Batch checks can be carried out on resists, silkscreen print elements, and a wide range of other elements relevant to manufacturing data.
Management of check data and referencing of error data is straightforward. Clicking an error report highlights the corresponding PCB area, allowing confirmation to be performed visually. Status information and comments can be added to error data.
Operating in real time as components are moved, this tool generates a temperature map display. Detailed analysis parameters for thermal conductivity calculation, temperature map accuracy, etc. can be specified.
Advanced Floor Planning and Routing
State-of-the-art floor planning is provided by CR-5000 Lightning Floorplan. Lightning is built upon five key concepts, combining unique technology for effective handling of complex design information, constraint and analysis engine unification, process orientation and frontloaded verification. It supports trade-off analysis from the circuit design stage, enabling design experimentation with full visibility of the impact on PCB layout and placement, and the effects on circuit electrical characteristics, plus full auto or interactive routing.
Package Predictor calculates the optimum die placement origin regardless of where the original was placed in the IC design tool. Once inside the system you can perform a number of helpful tasks to optimize net and die pad placement to ensure conductor escape. IC pin swaps that have been created can be back-annotated to the IC design tool for quick silicon updates. If changes to the die have been made, the changes can easily be reflected back into the design with net and bond wire updates ensuring accuracy and package reuse.
Package Synthesizer offers an intuitive, integrated environment for designing single, multi-, and stacked die packages for BGA, CSP, flipchip, as well as high density, advanced technology PCBs. It provides correct-by-design methodology, free-angle autorouting, including package-specific algorithms, design technology rules kits for build-up via structures, 3D design rules constraints (DRC) which adhere to manufacturing processes, constraint-driven, parametric bond shell generator, real time analysis and integration to 3rd party parasitic extraction and simulation tools (Ansoft TPA and HFSS products), and 3D interactive viewing.
Brochure: Interactive and Automating Routing
Board Designer gives you powerful and straightforward control over interactive routing – vital for dense PCBs with complex power distribution and test point requirements.1.01 MB
Datasheet: Board Designer
Zuken’s CR-5000 Board Designer is an intuitive, integrated environment for designing PCBs, BGAs and MCMs. With support of 3D utilities and viewers for HDI and advanced packaging, Board Designer offers one solution for all board technology needs.1.56 MB
Case Study: Renishaw gets better fit and impedance control for complex flexible PCBs in metrology instruments using CR-8000
Working in 3D for the first time, Renishaw’s PCB designers noticed a host of benefits, including fixing housing fit issues upfront and easier component placement.1.76 MB
Case Study: Rohde & Schwarz manages variants with increased efficiency using Zuken’s CR-5000 suite
Rohde & Schwarz manages variants with increased efficiency using Zuken’s CR-5000 suite. In a sophisticated design flow, the schematic provides a master data set that drives all PCB assembly variants.807.90 KB
Case Study: ARBURG - Getting designs right the first time
ARBURG is one of the world‘s leading manufacturers of injection molding machines.1.60 MB