CR-8000 Design Force
Zuken’s CR-8000 Design Force offers true co-design through a hierarchical setup wherein multiple designs can be brought together in the same framework. The connectivity between designs can be setup automatically or manually. The user is then able to move between designs (chip RDL, package or board or any combination thereof). This enables user to accurately see and edit the nets/routing on a system scale.
Design Force works natively in an OpenAccess environment and can bi-directionally exchange LEF/DEF files with IC layout tools. This allows co-design with chip-level design and manufacturing rules. Users can optimize I/O pin assignment bump and ball patterns, RDL and interposer routing, and die escape routing to improve signal performance, routability of signals across the system, and reduce layer cost at the chip, package and board level.
Supported Co-design Flows
Market driven engineering decisions require system co-design at a fast pace. Also, modern design flows incorporate a lot of design reuse necessitated by the fast pace of the market as well as efficient use of engineering resources. Zuken supports this important aspect through both a bottom-up and a top-down, wherein the user has the ability to drive decisions starting either from the chip to the board or the from the board on to the chip. This solution does away with file-hand-offs and the need to move between different tools, thus making for a seamless flow to optimize the bump- and ball- maps offering a true co-design experience.
The proliferation of packaging designs that combine multiple chips into a single package is creating new challenges for package, printed circuit board (PCB) and integrated circuits (IC) designers. The common practice of designing the package, PCB and IC in standalone environments requires time-consuming manual processes that are error-prone and limit the potential for design reuse.
The latest release of Zuken’s system-level PCB design environment, CR-8000, has received numerous enhancements aimed at ensuring performance, quality and manufacturability.
Toshiba Achieves Significant Product Size Reduction using 3D Chip, Package, Board Co-design in CR-8000 Design Force
Toshiba faced a difficult design problem: their TransferJet™ technology was embedded in a customer cell phone, and when the next rev of the phone came around, they learned that they needed to shrink the board from 8mm x 8mm to 4.5mm x 6mm, and they had to shrink the module thickness from 1.7mm to 1.0mm.
Advanced packaging techniques such as system-in-package (SiP), fan-out wafer-level packaging (FOWLP), 3D die stacks, etc. have been around for over a decade, yet with any other EDA design tool, it is still a tedious, time consuming, and error-prone process to implement these designs. It seems surprising that there are so few reliable EDA solutions out there, but CR-8000 Design Force is definitely the tool to look to when tackling advanced package design!
CR-8000 moves the architecture-optimized design seamlessly into detailed design, preserving all the architectural decisions without any data re-entry. Using CR-8000’s 3D PCB design platform, the system can be implemented and verified as a multi-board system with the MCAD enclosure.
This webinar is aimed to help the audience identify disconnects in the chip, package, and board design environment; and explore methods to optimize interconnects, improve design collaboration, and enable signal traceability and analysis across the complete system.
Pascal Nsame spent years at IBM, including stints on NASA’s first Mars Rover project, which is still in operation after 12 years (something no Mars Rover has ever done); the world’s most energy-efficient supercomputer project ranked #1 for more than 10 years; the memory sub-system of the IBM Watson Project, which was the first to compete and win against a human opponent in the Jeopardy question and answer quiz; and he’s named inventor or co-inventor on a host of patents.
As smart integrated technology connected to the internet becomes mainstream across the consumables industry, complex design challenges are no longer limited to the elite innovating companies, but spread to the far reaches of manufacturers who juggle the function, versus cost and competitive forces trade-off.
Thermal issues have long been one of the many Achilles heels in electronics design, in much the same way that electromagnetic noise and interference messes with your board. My blog post looks at how thermal dissipation is growing to be a much bigger beast than ever before as semiconductor companies and OSATs strive to better their products in the battle against time-to-market and better performance by stacking integrated circuits (ICs) in a package. Then I’ll be taking a look at how you can overcome thermal issues using new methodology through bringing the package, chip and board design environments together.
In this two part series of blog posts I’m going to talk about the design challenges of complex system-on-chips (SoCs) and through-silicon vias (TSVs), and how you can overcome many difficulties by using a 3D co-design environment.
Datasheet: Design Force - Chip, Package and Board Co-Design
Comprehensive system co-design recognizes the interaction between chip, package, and board data to reduce complexity, size and cost of the overall system.