Chip-Package-Board Co-design

Zuken’s CR-8000 Design Force offers true co-design through a hierarchical setup wherein multiple designs can be brought together in the same framework. The connectivity between designs can be setup automatically or manually. The user is then able to move between designs (chip RDL, package or board or any combination thereof). This enables user to accurately see and edit the nets/routing on a system scale.

Design Force works natively in an OpenAccess environment and can bi-directionally exchange LEF/DEF files with IC layout tools. This allows co-design with chip-level design and manufacturing rules. Users can optimize I/O pin assignment bump and ball patterns, RDL and interposer routing, and die escape routing to improve signal performance, routability of signals across the system, and reduce layer cost at the chip, package and board level.

Supported Co-design Flows

Market driven engineering decisions require system co-design at a fast pace. Also, modern design flows incorporate a lot of design reuse necessitated by the fast pace of the market as well as efficient use of engineering resources. Zuken supports this important aspect through both a bottom-up and a top-down, wherein the user has the ability to drive decisions starting either from the chip to the board or the from the board on to the chip. This solution does away with file-hand-offs and the need to move between different tools, thus making for a seamless flow to optimize the bump- and ball- maps offering a true co-design experience.

Co-design flow
Resources
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Webinar: I/O Optimization with 3D SoC, SiP, and PCB Co-design

This webinar is aimed to help the audience identify disconnects in the chip, package, and board design environment; and explore methods to optimize interconnects, improve design collaboration, and enable signal traceability and analysis across the complete system.

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Datasheet: Design Force - Chip, Package and Board Co-Design

Comprehensive system co-design recognizes the interaction between chip, package, and board data to reduce complexity, size and cost of the overall system.

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    I/O Optimization with 3D SoC, SiP, and PCB Co-design

    Chip Package Board Co-design

    Advanced Design Technologies

    Chip-Package-Board Co-design
    IC Package Design
    Hardware Architecture System Design