CR-8000 Resource Library
This webinar will discuss the challenges of producing a manufacturable Flex design as well as provide information on a tool based solution to address these challenges. Flex designs create challenges for most PCB tools in that the traditional PCB object checks do not account for the nuances of Flex checks.
This webinar will examine many of the concerns and challenges faced when producing release packages.
This webinar is Part 3 of a 3 part series covering the systems engineering process of converting product or system requirements into a viable and robust hardware architecture and then moving that architecture directly into detailed design without any manual re-entry.
This webinar is Part 2 of a 3 part series covering the systems engineering process of converting product or system requirements into a viable and robust hardware architecture and then moving that architecture directly into detailed design without any manual re-entry.
This webinar is Part 1 of a 3 part series covering the systems engineering process of converting product or system requirements into a viable and robust hardware architecture and then moving that architecture directly into detailed design without any manual re-entry.
In this webinar we will explore the process for performing a quick EMC analysis followed by a more in-depth EMC analysis driven by properties assigned during schematic capture.
This webinar will discuss and demonstrate the key concepts behind a 3D multi-discipline design where supplychain, PCB, MCAD and analysis all converge into a next generation design process.
This webinar will demonstrate a virtual prototyping solution that validates a set of product requirements against a proposed detailed design.
This webinar will demonstrate how next generation ECAD software is being used to address the IP theft challenge with permission controls that enable users to define with a high level of granularity the design information that will be included and excluded from the published data set.
During this webinar we will demonstrate how to create, manage and grow an engineering knowledge base, and use that information to greatly improve your PCB design process.
Traditional schematic entry tools offer the ability to create a single logical design to drive a single PCB layout.
The webinar will explore various points in the design flow where co-design of the FPGA and board layout can take place; this includes library part creation, schematic entry, I/O optimization and pin assignment management during board layout. See how a FPGA / PCB co-design process can improve overall design quality in less time.
This webinar explores how to realize a DDR3 system using constraints and validate the design’s timing margins.
This webinar is aimed to help the audience identify disconnects in the chip, package, and board design environment; and explore methods to optimize interconnects, improve design collaboration, and enable signal traceability and analysis across the complete system.
This session presents aspects of achieving good power integrity by defining key concepts, showing example layouts, and using PI analysis tools to help better understand PI effects and mitigation techniques.
This webinar will present an approach to make ECAD / MCAD collaboration part of your standard design process. Easily import MCAD data and orient multiple PCBs within the enclosure and detect collisions. Make corrections and re-analyze.
Design rework can cost you time and money. And going back and forth between ECAD and MCAD departments takes time.
Often, the planning of an electronic system is done with disparate tools that were not designed for electronic system planning. This is not only inefficient, requiring many workarounds, but later forces you to re-enter your design planning data into the design authoring tools.
The advent of the Internet of Things (IoT) offers the potential to automatically collect detailed performance information from every device in the field at minimal cost.
This white paper explores the benefits of bringing all these design domains together in a single tool that enables the translation of product requirements into an initial hardware architecture, ready for detailed design.
The electronic product design process is being challenged like never before, with the need to develop feature-rich, light, compact products at a lower cost in less time.
This white paper explores the benefits of product-centric design and how it differs from current-generation PCB-centric processes and tools.
Intellectual property (IP) theft is an ever-present danger to companies who subcontract manufacturing to electronic manufacturing services (EMS) providers.Read More
Mecalac (Formerly Terex GB) Cuts the Time Taken to Develop Right-First-Time Cable Harnesses for Its Heavy Plant Vehicles
Mecalac Construction Equipment UK is a global manufacturer of compact plant machinery, providing market-leading solutions that maximize return on investment.Read More
Toshiba Achieves Significant Product Size Reduction using 3D Chip, Package, Board Co-design in CR-8000 Design Force
Toshiba faced a difficult design problem: their TransferJet™ technology was embedded in a customer cell phone, and when the next rev of the phone came around, they learned that they needed to shrink the board from 8mm x 8mm to 4.5mm x 6mm, and they had to shrink the module thickness from 1.7mm to 1.0mm.Read More
Endress+Hauser Standardizes PCB Engineering and Production Processes for Industrial Measurement Products Across Distributed Locations
Endress+Hauser is a global leader in measurement instrumentation, services and solutions for industrial process engineering.Read More
Renishaw Gets Better Fit and Impedance Control for Complex Flexible PCBs in Metrology Instruments using CR-8000
Working in 3D for the first time, Renishaw’s PCB designers noticed a host of benefits, including fixing housing fit issues upfront and easier component placement.Read More
Rohde & Schwarz Manages Variants with Increased Efficiency using Zuken's CR-5000 Suite
Rohde & Schwarz manages variants with increased efficiency using Zuken’s CR-5000 suite. In a sophisticated design flow, the schematic provides a master data set that drives all PCB assembly variants.Read More
ARBURG - Getting Designs Right the First Time
ARBURG is one of the world‘s leading manufacturers of injection molding machines.Download
Datasheet: System Planner
System Planner is a system-level design environment for architecture of electronics systems and products.Download
Datasheet: CR-8000 Library
The use of common library data throughout the whole design cycle is an essential element of the CR-8000 constraints-driven, right-by-construction methodology.Download
Datasheet: Advanced Design for Manufacturing (ADM)
In the design and production of electronic products, manufacturability checks are difficult to perform manually and are often made after the design process has been completed.Download
Datasheet: Graphical Pin Manager - FPGA/PCB Co-design
Engineers continue to embrace programmable logical devices within their product designs in numerous applications across a wide range of industries.Download
Datasheet: Design Force - Chip, Package and Board Co-Design
Comprehensive system co-design recognizes the interaction between chip, package, and board data to reduce complexity, size and cost of the overall system.Download
Datasheet: Design Gateway - Circuit Engineering
Design Gateway is Zuken’s platform for logical circuit design and verification of single and multi-board system-level electronic designs.Download
Datasheet: Circuit DR Navi - Engineering Knowledge
CR-8000 Circuit DR Navi helps design teams consolidate engineering expertise and best practices into a central repository integrated with the design process.Download
Datasheet: Design Force - Advanced Packaging
Traditional two dimensional design tools often fall short when it comes to studyingthe structure and routability of the advanced packages required for today’scomplex designs.Download
PCB Library and Design Data ManagementDownload
Design Force - Multi-board System Design
Design Force fully leverages the latest industry hardware and software capabilities, allowing users to design in a native 3D environment, obtaining optimal performance by utilizing native 64-bit, multi-threading, multi-core processors.
Even though power integrity strategies are now discussed on a daily basis, power distribution design is still a third order design aspect, done late in the design. It involves often a “design-by-hope” approach doing a copper pouring of the power-templates, and additionally sprinkling the board with decoupling capacitors. Such traditional methods of designing complex PCBs, and their power distribution systems (PDS) in particular, cost companies time and money in both the design and manufacturing stages.
Creating pin pairs in the Constraint Browser is fine for one or two nets at a time, but if you want to create pin pairs for a whole design, I recommend using an easy, single-step macro.
Did you know when editing lengthening patterns in CR-8000 Design Force, you can modify the lengthening pattern, and meet your constraints all in one step
XJTAG has partnered with Zuken create a new plugin for Design Gateway and is offering it free of charge. The plugin, called XJTAG DFT Assistant, helps to validate correct JTAG chain connectivity, while displaying boundary scan access and coverage onto the schematic diagram through full integration with Design Gateway. So if you are using boundary scan today or want to incorporate it in your next design, the XJTAG DFT Assistant plugin is a tool you should be using.
Flex designs pose unique challenges for most PCB tools because traditional object checks don’t account for Flex check nuances. They present a new set of objects that are best accounted for during the design phase.
When it comes design rule checks for PCB designs, there are checks that should be performed that are just as important as spacing rules. Strict adherence to basic PCB design rule checks, such as track to track, track to via, via to via, pad to track etc. – though necessary to avoid short circuits – only scratch the surface when trying to identify potential design flaws. I often see PCB designs that are completed based on this premise and wonder what else could be hiding in the design?
CR-8000 Design Force 2017 has improved the offset via function by adding efficiency in pulling out tracks from vias, creating BGA designs and build-up designs.
A common task that is often dreaded among PCB designers is having to relocate a large point-count BGA that’s fanned out, and even partially escaped routed, to the opposite side of a PCB.
Advanced packaging techniques such as system-in-package (SiP), fan-out wafer-level packaging (FOWLP), 3D die stacks, etc. have been around for over a decade, yet with any other EDA design tool, it is still a tedious, time consuming, and error-prone process to implement these designs. It seems surprising that there are so few reliable EDA solutions out there, but CR-8000 Design Force is definitely the tool to look to when tackling advanced package design!
This is an exciting time in the product development world. Increasing product complexity is driving the need for a design process evolution. Not long ago the detailed design process was the centerpiece of product development. But the need for functional and physical design accuracy is forcing the product development process to evolve. In response, the product development process is both converging and expanding.
How Virtual Prototyping Tools Can Help Decide if Fan-out Wafter-level Packaging is Right for Your Product
Put simply, FO-WLP establishes die-to-die and die-to-ball grid array (BGA) connectivity directly through packaging redistribution layers (RDLs), eliminating the packaging substrate used in more-established flip-chip and wafer-level chip scale packages (WLCSP).
When it comes to advanced miniaturization of electronic products such as wearables and mobile devices, it is crucial that your design process utilize tools that meet and exceed engineering requirements. In this video, we will show how embedded passive devices are created and how they can be moved from layer to layer in Design Force.
If you haven’t noticed, the electronic design process is evolving with the rise of Model-Based Systems Engineering (MBSE) and the demands of the Internet of Things (IoT). The standard 2D single board PCB design process can’t keep up with the demands of system-level design required by today’s more complex products.
Defining initial hardware architecture requires many decisions, most of which impact a variety of different stakeholders and requirements – including multiple design tools – circuit design, PCB layout, mechanical design, spreadsheets, etc. that are used to track different elements of the design. It sometimes seems that by the time you determine the impact of a decision on all the requirements, the design has changed to a point that your decision is irrelevant.
Original equipment manufacturers (OEMs) can easily feel like a kid in a candy store with so many recently developed manufacturing technologies to choose from. There’s flex boards, rigid flex hybrids, chip on board, embedded components, low temperature co-fired ceramic, to name a few. Each of these technologies offers its own unique mix of functionality, cost, size, weight, delivery time and other benefits.
After a lengthy quiet period, the hardware design process is suddenly experiencing numerous changes in the form of design discipline convergence and process extension. The widely used 2D single board PCB detailed design process is being replaced by a 3D multi-board and multi-discipline one. What is happening in detailed design is a great blog topic, but I want to talk about what is happening upstream from the detailed design process – hardware architecture design.
We all know that manufacturing yields and costs are the driving force behind product development, rather than product quality. You can buy a Design for Manufacturing (DFM) tool, but try buying a Design for Quality tool – good luck! The best way of measuring product quality is finding out how your product performs in the hands of the customer. But measuring product performance, and quantifying quality, is difficult at best for most products.
Not long ago, third dimension issues didn’t figure too much in high-speed design calculations; but signals have become so fast that those vias don’t affect them the same way they did before. Those really fast signals have become part of super-common bus standards that are used in all kinds of products.
Pascal Nsame spent years at IBM, including stints on NASA’s first Mars Rover project, which is still in operation after 12 years (something no Mars Rover has ever done); the world’s most energy-efficient supercomputer project ranked #1 for more than 10 years; the memory sub-system of the IBM Watson Project, which was the first to compete and win against a human opponent in the Jeopardy question and answer quiz; and he’s named inventor or co-inventor on a host of patents.
Modern PCB designs have IOs reaching speeds of multi Gigabits per second, making signal integrity analysis an imperative for any product in the design phase. As the industry spends increasing amounts of time on finding and fixing these issues, it’s worthwhile any designers out there that are not already doing so, investing some energy in reducing design cycle time through early identification of high speed issues like crosstalk and return path discontinuity etc. Let me go into why it’s worth your effort…
What does it take to develop a successful new product in today’s highly competitive global electronics marketplace? It all starts with a systems architect tasked with seamlessly moving between the many different disciplines – functional block diagramming, floor planning, space planning, cost estimating, etc. required to define the hardware architecture. This special guy or gal then must work the magic needed to define a hardware architecture that meets all of the targets – functionality, cost, weight, style, battery life, etc. – required to ensure that success of the product.
Although we’ve been talking about it for years, in PCB design it has yet to catch on in quite the same way despite there being a host of benefits to be reaped from modular design practices. So in the first of this two-part series I’d like to challenge you to ask yourself a few questions about how you reuse designs.
As smart integrated technology connected to the internet becomes mainstream across the consumables industry, complex design challenges are no longer limited to the elite innovating companies, but spread to the far reaches of manufacturers who juggle the function, versus cost and competitive forces trade-off.
Thermal issues have long been one of the many Achilles heels in electronics design, in much the same way that electromagnetic noise and interference messes with your board. My blog post looks at how thermal dissipation is growing to be a much bigger beast than ever before as semiconductor companies and OSATs strive to better their products in the battle against time-to-market and better performance by stacking integrated circuits (ICs) in a package. Then I’ll be taking a look at how you can overcome thermal issues using new methodology through bringing the package, chip and board design environments together.
You’ll already be well aware that EMC compliance is a necessary condition for releasing products to market. There’s National and International bodies such as the IEC and the FCC that define limits on how much a device is allowed to produce, and the how stringent these are will vary according to industry.
Which is a little like what you get with the latest update of CR-8000 Design Force. Instead of using stylized shapes defined by boundary boxes, CR-8000 Design Force now uses a true 3D component model with a precisely-matched 3D shape, making enclosure collision checks and 3D clearance checks much more accurate. And making fastening the enclosure lid straightforward.
A new generation of 3D multi-board product-level design tools manages multi-board placement in both 2D and 3D and enables co-design of the chip, package and board in a single environment. Multi-board design makes it possible to create and validate a design with any combination of system-on-chips (SoC), packages and PCBs as a complete system. Chip-package-board co-design enables designers to optimize routability via pin assignment, and I/O placement to minimize layer counts between the package, chip and board. The new design methodology makes it possible to deliver more functional, higher performing and less expensive products to market in less time.
Within the engineering environment the above Latin phrase correlates well with new product development. As design cycles condense and first pass success becomes essential, the need to ensure that engineering requirements, best practices, design guidelines and lessons learned are all properly used to drive product development becomes paramount. Repeating the same mistakes, missing key requirements, and failure to follow design guidelines all cost time and money.
Today I’m going to be talking about the gradual convergence of EDA single tools to integrated systems. In the early days of HiFi home entertainment systems, specialist vendors provided separate record (vinyl!) decks, amplifiers and speakers, then left it to the ingenuity of the customer to build their own system – they still do for the serious audiophiles.
In this two part series of blog posts I’m going to talk about the design challenges of complex system-on-chips (SoCs) and through-silicon vias (TSVs), and how you can overcome many difficulties by using a 3D co-design environment.
As companies benefit from the global supply chain in terms of lower production costs and faster turnaround times, they are also exposing their intellectual property to third parties, including PCB design data.
In my time working with companies in the automotive, telecom/wireless and defense industries, I often hear of the many issues facing design teams as they tackle projects made-up of multiple PCBs connected by flexible PCBs, cables, or with a backplane board. Often, the challenge arises when defining and implementing the interconnects across boards, and managing changes throughout the course of the PCB design process. Today I’m going to share with you, my top tips for overcoming these issues.
It’s no secret that placing passive devices in the proper location, whether it is nearer to the source/driver or the receiver/load pins, makes the difference between poor signal integrity and optimal signal integrity. Often this can be impacted by a breakdown in communications between circuit designers and PCB designers.
Incorporating FPGAs into PCBs designs can be tricky and involves a constant dialog of communication between the FPGA designer and design and PCB/layout designer throughout the process – which can be tiresome, tedious and, worst of all, time-consuming.
Design Products, Not Just Boards
ECAD XVII - Comparing Layer Stackups of Zuken and ANSYS
ECAD XVI - CR-8000 Design Force to ANSYS Slwave
ECAD XVII - CR-8000 Design Force to Slwave via EDB
Design Force Movies
ECAD/MCAD Integration: Align PCB with Enclosure
ECAD/MCAD Integration: Configure Multi-board
ECAD/MCAD Integration: 3D Collision and Clearance Checking
Power Integrity Analyzer
Automatic Tuning of Differential Pairs
Design Force to AWR Microwave Integration
System-level PCB Design Environment
Design Gateway Movies
Evaluating Signal Continuity across a Product-level Schematic
Zuken® and XJTAG®, a leader in boundary scan and design for test technology, have releas...February 22, 2018
Zuken has expanded its partnership with SamacSys to enable engineers and designers to down...December 13, 2017
Zuken and Nano Dimension will share a booth and showcase the latest technologies for PCB D...September 6, 2017
Zuken USA, Inc, is now accepting abstracts for Zuken Innovation World (ZIW) 2018, to be he...August 17, 2017
XJTAG DFT Assistant will help to validate correct JTAG chain connectivity while displaying...July 19, 2017
This latest release is the first to enhance electrical and electronic co-design at the arc...July 11, 2017
Zuken and Nano Dimension are working together to advance the 3D printing user experience a...April 5, 2017
Zuken has partnered with SamacSys to help companies develop component libraries rapidly, f...January 25, 2017
Kardinal Microsystems has joined Zuken USA’s Startup Partner Program aimed at early to m...August 17, 2016
The CR-8000 2016 release expands ANSYS support beyond the existing ANSYS neutral file (ANF...June 16, 2016
Engineers facing extremely tight design cycles will benefit from powerful new multi-user f...June 7, 2016
Zuken announces that the Microsoft Devices division has selected Zuken’s DS-2 engineerin...May 10, 2016
Zuken’s CR-8000 and CR-5000 PCB design platforms will now offer users access to more tha...April 13, 2016
Zuken Helps Designers Get Better Product Enclosure Fit with True 3D Component Shapes in CR-8000 Design Force
This latest version of Zuken’s CR-8000 single and multi-board design solution also inclu...September 15, 2015
Synopsys sought the highest-performing PCB design platform available to assist with design...September 2, 2015
Zuken announces that electronics manufacturing services (EMS) provider Enics has invested ...July 14, 2015
Zuken announces that board reference designs for Intel-produced Internet of Things (IoT) d...April 1, 2015
Zuken Inc. has announced that major Taiwanese Design and Manufacturing Services (DMS) comp...September 16, 2014
By integrating SiSoft’s advanced signal integrity solutions for state-of-the-art, high-s...August 19, 2014
Zuken’s Humair Mandavia and Steve Watt have been honored by IPC for their contribution t...May 8, 2014
Zuken continues to add new team design capabilities...April 24, 2014