FPGA Pin Optimization
CR-8000 Graphical Pin Manager (GPM)
Zuken’s Graphical Pin Manager (GPM), offers an effective FPGA/PCB co-design environment providing support for the latest devices offered by FPGA vendors, such as Xilinx, Altera, Lattice, and Microsemi. As part of the CR-8000 family, GPM enables design teams to communicate I/O and constraint information intelligently for FPGAs or other high-pin count devices, at any time, using Design Gateway and Design Force. This means programmable devices can be developed in parallel to the PCB design, and are ready to meet project delivery and production schedules.
FPGA designers and librarians can import pin assignment information directly from FPGA design suites such as Altera Quartus II, Xilinx ISE, Microsemi Libero, Lattice + ispLEVER/Diamond and Aldec Active-HDL, or alternatively use BSDL, VHDL/Verilog or CSV files. GPM also offers an extensive library of FPGA vendor device kits for Altera, Xilinx, Microsemi and Lattice, providing additional key attributes for I/Os, such as differential pairs, pin type, I/O bank and power/ground assignments. Zuken offers up-to-date device kit downloads from our website to access the latest devices from FPGA vendors.
Once part information is loaded into GPM, users access easy-to-use wizards to automatically divide and generate symbols for immediate use in logical circuit design. GPM is also integrated with the library, so users can easily associate the required physical footprints and export directly to the library for fast part creation. Once the pin assignment is defined in GPM, the pin report file is exported to the FPGA design tools.
As the initial FPGA is simulated and synthesized, engineers can load the logical and physical circuit design within GPM. Engineers may review the current pin assignment and each of the constraints and rules associated with each I/O, then use the extensive set of utilities to visualize the FPGA on the PCB. The FPGA can be viewed with colored I/O banks, or as the sub-element model defined when dividing the component. This means analyzing the FPGA structure and identifying how interconnects relate to other components is straightforward.
GPM also provides a ratsnest view of the board, showing the connection between pins and from partially routed signals. For rules-driven optimization of the I/Os, users can conduct pin swaps interactively, using visual indicators to highlight the candidates for swapping with the selected net. The automatic pin assignment optimization feature then untangles the ratsnest for the selected FPGA components.
GPM is also compatible with CR-5000 System Designer and Board Designer.
You can tell when something isn’t as clear as it should be. The same questions come up time and again. You ask three experts and get three different answers. Routing differential pairs can be like that. Why? Because “it depends” – on exactly what signals those pairs are carrying and what kind of PCB you’re creating.
The webinar will explore various points in the design flow where co-design of the FPGA and board layout can take place; this includes library part creation, schematic entry, I/O optimization and pin assignment management during board layout. See how a FPGA / PCB co-design process can improve overall design quality in less time.
Although we’ve been talking about it for years, in PCB design it has yet to catch on in quite the same way despite there being a host of benefits to be reaped from modular design practices. So in the first of this two-part series I’d like to challenge you to ask yourself a few questions about how you reuse designs.
It’s no secret that placing passive devices in the proper location, whether it is nearer to the source/driver or the receiver/load pins, makes the difference between poor signal integrity and optimal signal integrity. Often this can be impacted by a breakdown in communications between circuit designers and PCB designers.
Incorporating FPGAs into PCBs designs can be tricky and involves a constant dialog of communication between the FPGA designer and design and PCB/layout designer throughout the process – which can be tiresome, tedious and, worst of all, time-consuming.