IC Package Design
As IC packaging architecture advances, Zuken’s Design Force enables the designer to deal with the growing complexity in design space in handling high pin-counts, high density designs and the need to interface with multiple formats and flows. Parametric wizards are available to define and optimize pin maps. A native 3D interface is available to deal with the various package architectures allowing for seamless co-design with chip and PCB designs. For feasibility studies, automatic fan-out and full routing features are available.
The unique system-level capabilities of Design Force enable design teams to conduct path finding and feasibility studies earlier in the design process by creating or reusing design data, or through approximate models. With a true co-design platform, designers can conduct rapid and accurate exploration of the true interconnect structure, carry out concurrent signal and power integrity analysis, or interface to best-in-class tools.
Supported Package Architectures
- Filp Chip
- Package-on-Package (PoP)
- System-in-Package (SiP)
- High Density Advanced Packaging (HDAP)
- Fan-in Wafer-Level-Packaging/Wafer-level Chip Scale Package (WLCSP)
- Fan-out Wafer level packaging (FOWLP) and many more…
White Paper: 3D Convergence of Multi-board PCB and IC Packaging Design
The electronic product design process is being challenged like never before, with the need to develop feature-rich, light, compact products at a lower cost in less time.Download
Datasheet: Design Force - Advanced Packaging
Traditional two dimensional design tools often fall short when it comes to studyingthe structure and routability of the advanced packages required for today’scomplex designs.