IC Package Design
As IC packaging architecture advances, Zuken’s Design Force enables the designer to deal with the growing complexity in design space in handling high pin-counts, high density designs and the need to interface with multiple formats and flows. Parametric wizards are available to define and optimize pin maps. A native 3D interface is available to deal with the various package architectures allowing for seamless co-design with chip and PCB designs. For feasibility studies, automatic fan-out and full routing features are available.
The unique system-level capabilities of Design Force enable design teams to conduct path finding and feasibility studies earlier in the design process by creating or reusing design data, or through approximate models. With a true co-design platform, designers can conduct rapid and accurate exploration of the true interconnect structure, carry out concurrent signal and power integrity analysis, or interface to best-in-class tools.
Supported Package Architectures
- Filp Chip
- Package-on-Package (PoP)
- System-in-Package (SiP)
- High Density Advanced Packaging (HDAP)
- Fan-in Wafer-Level-Packaging/Wafer-level Chip Scale Package (WLCSP)
- Fan-out Wafer level packaging (FOWLP) and many more…
Advanced packaging techniques such as system-in-package (SiP), fan-out wafer-level packaging (FOWLP), 3D die stacks, etc. have been around for over a decade, yet with any other EDA design tool, it is still a tedious, time consuming, and error-prone process to implement these designs. It seems surprising that there are so few reliable EDA solutions out there, but CR-8000 Design Force is definitely the tool to look to when tackling advanced package design!
How Virtual Prototyping Tools Can Help Decide if Fan-out Wafter-level Packaging is Right for Your Product
Put simply, FO-WLP establishes die-to-die and die-to-ball grid array (BGA) connectivity directly through packaging redistribution layers (RDLs), eliminating the packaging substrate used in more-established flip-chip and wafer-level chip scale packages (WLCSP).
The electronic product design process is being challenged like never before, with the need to develop feature-rich, light, compact products at a lower cost in less time.
As smart integrated technology connected to the internet becomes mainstream across the consumables industry, complex design challenges are no longer limited to the elite innovating companies, but spread to the far reaches of manufacturers who juggle the function, versus cost and competitive forces trade-off.
Thermal issues have long been one of the many Achilles heels in electronics design, in much the same way that electromagnetic noise and interference messes with your board. My blog post looks at how thermal dissipation is growing to be a much bigger beast than ever before as semiconductor companies and OSATs strive to better their products in the battle against time-to-market and better performance by stacking integrated circuits (ICs) in a package. Then I’ll be taking a look at how you can overcome thermal issues using new methodology through bringing the package, chip and board design environments together.
A new generation of 3D multi-board product-level design tools manages multi-board placement in both 2D and 3D and enables co-design of the chip, package and board in a single environment. Multi-board design makes it possible to create and validate a design with any combination of system-on-chips (SoC), packages and PCBs as a complete system. Chip-package-board co-design enables designers to optimize routability via pin assignment, and I/O placement to minimize layer counts between the package, chip and board. The new design methodology makes it possible to deliver more functional, higher performing and less expensive products to market in less time.