CR-8000 Past Versions

CR-8000 2017 is the first release to enhance electrical and electronic co-design at the architectural design phase. CR-8000 improves multi-board system optimization through new module management capabilities in System Planner 2017, and contains more than 150 user-driven enhancements and new features.

CR-8000 2017

ECAD/MCAD Collaboration

Electrical co-design is added to the architecture design phase through direct export to E3.series, Zuken’s electrical design tool suite. This new capability enables cross-domain architecture optimization, and eliminates the need for data reentry. With the rise in products containing both electronic and electrical design objects, the need for tight design integration across the domains becomes increasingly urgent.

Information on wires between boards can now be output in E3.WDG format. With this process integrated into the system instead of being managed as a manual task, errors may be identified earlier in the design process saving costs and improving quality.

Logical Visionary Connector Pair Setting (Terminal Pin Assignment)

Drawing board or unit connectivity diagrams allow signals between boards and/or units to be studied. Defining the matching pins from the harness pin to the pin connector is done automatically, improving quality over manual matching. Pin pair information can be set for male and female connectors.

Architecture Design Expands Library and Modular Design Support

Module and detailed design integration is improved through modular design. Design module status can be verified to detect updates based on a set of user-defined rules. In addition, partitioning a design module across blocks or boards is now possible on a schematic page basis, allowing for improved architectural design optimization.

Reference designator assignments can be made, or auto-generated, during architecture design on a block-by-basis, allowing for more collaboration with detailed design. Design rule checks can also be applied to manage unassigned or duplicate reference designators. During physical optimization, components within the functional block may be identified and moved as a single unit, making floor planning easy and efficient.

Import 3D Component Shape Specified in CDB

Module and detailed design integration is improved through modular design. Design module status can be verified to detect updates based on a set of user-defined rules. In addition, partitioning a design module across blocks or boards is now possible on a schematic page basis, allowing for improved architectural design optimization.

Import 3D Component Shape Specified in CDB

DRC and ERC at Electrical Net Level

Design rule checks (DRC) and electrical rule checks (ERC) at electrical net level check are supported. DRCs now look at one or more electrical nets, offering much more electrically intelligent and robust rule checks.

Import 3D Component Shape Specified in CDB

Circuit Connectivity Information List

The IC connectivity cross reference check function allows the connectivity of the circuit design to be reviewed.

Import of MCAD Data Efficiency Improvements

MCAD co-design has been expanded by importing figures from a board model created using mechanical CAD. Supported systems include CATIA V5, Creo, NX, SolidWorks, STEP, Parasolid, and ACIS. More accurate and speedier designs are possible using this level of mechanical detail.

The following data can be imported to design data: Board outline; Hole (Round hole, slot hole, rectangular hole, non-circular hole); Height limit area, area fill; Arrow view from the top or bottom of a component shape; Component coordinates.

Bump Line Function for Skew Control

Skew adjustment control is possible using ‘bump line’, both in style and type, while maintaining impedance differential.

  • Enhancements made to the Edit function
  • Improvement to efficiency in skew adjustment for route differential pairs
  • Additional function to delete all, or selected bump lines

Support for 3D PDF using PRC

Enhancements have been made to the 3D Model Export function to allow export of PRC data for subsequent output as a 3D PDF using third party software.

Improved PI and DC Analysis Flows

Enhancements to the PI/EMI Analysis Tool include a refreshed GUI and streamlined workflows improving the efficiency for PI and DC analysis.

Analysis Result Output in DC Passives

Analysis results, such as voltage drops, are now measured and shown on passive device ports explicitly similar to other DC analysis results.

What-if Analysis Using a Virtual Decoupling Capacitor

A decoupling capacitor can now be virtually added without changing the circuit configuration, making selecting the decoupling capacitor more efficient.

CR-8000 2016 screenshotZuken’s CR-8000, the industry’s only product-centric design solution, continues to lead the way with next-generation tools capable of creating today’s and tomorrow’s complex product designs.

CR-8000 2016 helps engineers facing extremely tight turnarounds with its powerful new multi-user functionality. Concurrent multi-area PCB design reduces design time, meaning quicker time-to-market. In addition, a raft of native 3D design enhancements offer more efficient ECAD/MCAD task management and design re-use, plus functionality to enable early validation to reduce iterations and improve design quality.

CR-8000 is the complete solution for your system-level, single and multi-board design requirements. In addition to the features highlighted below, further information is available in the product release notes.

CR-8000 ANSYS SupportCR-8000 2016 expands ANSYS support beyond the existing ANSYS neutral file (ANF) format to include EDB, enhancing the simulation interface with Design Force, Zuken’s PCB design tool, ANSYS® HFSS™ software and ANSYS® SIwave™ software.

Using EDB in Design Force 2016, users can easily pass extensive information to support simulation, such as ports, boundary definitions and simulation control parameters to the ANSYS platform. CR-8000’s support for the EDB will deliver a unique virtual prototyping flow to simulate electromagnetic, thermal, and mechanical behavior of a product, allowing design engineers to meet their system power and performance targets, while reducing cost.

Concurrent Multi-area PCB Design

Engineers facing extremely tight turnarounds will benefit from powerful new multi-user functionality. Teams can work on the same design area, in the same product, at exactly the same time. Designs can be modified simultaneously, reducing the overall design time and making best use of globally-dispersed teams. Each engineer can control their own viewpoint, has continual and instantaneous visibility of the design, and any remaining unconnected nets.

Performance improvements in both the client and server offer design speeds of up to 17 times faster.

Efficient Management of Design Changes and Obsolescence

Design effort is dramatically reduced with improved part swap capability. Superseded or highlighted parts can be viewed directly within the circuit data, and changed collectively. This avoids time-consuming manual checks for part swaps, and enables designers to start the design at any point swapping out parts as the design progresses without building up time-consuming amendments and worrying about quality issues by missing an instance of a superseded part.

Modular Circuit Design

The circuit block library can be searched and re-used, which offers increased a more streamlined and simple design process. Component frame or grouping helps manage re-use block elements. Building on existing constraint re-use functionality, constraint arbitration allows users to view a section of the block and easily see conflicting constraints, as well as define which information to preserve within a design by constraint or object.

3D Product Design Enhancements

True component shapes are now defined within the library at footprint, package, part and instance level, in addition to existing support in PCB design.

Origin alignment is managed, ensuring a common reference point between the ECAD and MCAD libraries and alignment of the 3D shape to the component footprint.

With rigid-flex product visualization and design validation checks, the bend of the flex board can be modeled and collisions viewed to check design issues with the product modeled to final state condition. This avoids design re-work and iterations between mechanical and electrical design.

Design Data Sharing

An accurate 3D component model of output to MCAD is supported, with export of a whole or subset of the design. MCAD data import versions have been updated:

  • IPC-2581 output modes for inspection & design
  • ODB++ import and export updates
  • Ansys Electronic DataBase (EDB) format support

Chip-Package-Board Co-design

Performance improvements mean support is now available for very large pin count devices. In addition, support for the latest LEF/DEF format (v 5.8 import/export) is available. Designers can create components directly from semiconductor design data.

Design Analysis Improvement

Analog simulation is strengthened with an interface to Linear Technologies. LTSpice is a powerful, fast and mainstream simulation tool, schematic capture and waveform viewer with enhancements and models for improving the simulation of switching regulators.

New SI analysis features include:

  • Package model and algorithmic modeling with IBIS-AMI
  • Frequency domain analysis from electrical editor
  • Improved S-parameter support, with results display and export capability.

Improved Test Point Support

Test points can be allocated automatically at all stages of the design process, saving designers time. Back annotation of test points is achieved, with information assigned to the nearest component pin.

Design Efficiency

Real-time routing information is enhanced, with designers receiving visual confirmation of constraint compliance. SI/PI and EMI analysis is improved:

  • IBIS-AMI support
  • S-parameter display and export
  • Package model assignment at buffer model symbols
CR-8000 Clearance Checks

True 3D component shapes are used for collision checks and 3D clearance checks

Zuken’s CR-8000, the industry’s only product-centric design solution, continues to lead the way with next-generation tools capable of creating today’s and tomorrow’s complex product designs. CR-8000 2015.1 helps product designers meet the challenges of today’s ever-smaller and complex enclosures, with 3D clearance analysis using true component shapes. It also includes improved accuracy in layer configuration design work through transfer of layer configuration data between CR-8000 Design Force and Polar Instruments Speedstack.

CR-8000 is the complete solution for your system-level, single and multi-board design requirements. In addition to the features highlighted below, further information is available in the product release notes

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Clearance analysis to a true component shape

Specified shapes

Specified shapes are assigned individually or collectively.

Perform more accurate 3D checks by using a true 3D component model with a precisely-matched 3D shape. Accurate shape parts can be used for track changes, collision checks and 3D clearance checks, offering more accurate results than tests performed with shapes defined by a boundary box. Features include:

  • Multi-board clearance and enclosure checking
  • Specified shapes are assigned individually or collectively
  • Product level design with measurements (USP)
  • Major CAD formats are supported, including: STEP, CATIA, Creo, NX, SolidWorks, Parasolid and ACIS.

Benefits

  • Reduce the risk of prototype reworking at the manufacturing stage because of a fit problem.
  • Better design flow between electrical and mechanical design, reducing the silo effect.

Detail board stackup design and specification

Design Force and Polar Instruments Speedstack

Layer configuration data can now be transferred between Zuken’s CR-8000 Design Force and Polar Instruments Speedstack

Layer configuration data can now be transferred between Design Force and Polar Instruments Speedstack, removing the need to re-input stackup data in Speedstack. In addition, the results of review in Speedstack can be used for board design in Design Force. This ensures designs are created using the most accurate information shared with manufacturers.

Benefits

  • Improved efficiency in layer configuration design.
  • Material suppliers values are used for values such as dielectrics – no more interim estimates.
  • Closer collaboration between manufacturing and PCB design – no manual data flow and checking.

User productivity and efficiency enhancements

Design edit function enhancements

Track routing

During routing with the Track/Route Differential Pair/Bundle Route command, the track width changes automatically on the boundary of a rule area.

Lines with different widths can now be connected smoothly using arcs. It is now easy to create line shapes considering the production yield ratio and signal quality.

Routing Function Enhancements

Improved support for track input functions:

  • During routing with the track/route differential pair/bundle route command, the track width now changes automatically on the boundary of a rule area.
  • Providing a more accurate and controllable routing – leading to better signal integrity characteristics

Improvements to Operability

  • Full file paths are now displayed in [Recent Files], and the number of files displayed in [Recent Files] can now be increased.
  • Improved Area Fill Editing Operability
  • Editing operations on an area fill can now be started by double-clicking on it. Commands can be switched easily with less movement of the mouse

Enhancements to the SI analysis function

  • Waveforms in the waveform viewer can now be output to an image file in bmp/png/jpg format improving efficiency in documenting and reporting signal results for engineering information and review
  • Enhancements to Board List Processor
  • New function processes the output format of the info list.
  • Number of information units and items that can be output from the board list processor has been increased.

Zuken’s CR-8000, the industry’s only product-centric design solution, continues to lead the way with next-generation tools capable of creating today’s and tomorrow’s complex product designs. CR-8000 2015 offers many enhancements to make team and cross-discipline collaboration even more straightforward.

CR-8000 is the complete solution for your system-level, single and multi-board design requirements. In addition to the features highlighted below, further information is available in the product release notes.

General

Engineering Desktop design portal enhancements

The CR-8000 Engineering Desktop is a design portal common to CR-8000 products. The portal can manage designs, files, and launch applications for all of the major CR-8000 products, along with CR-5000 System Designer, Board Designer, and Lightning.

System Planner

System-level product design

System product design

System product design containing multiple boards, circuit and geometric design data.

Create a product of a number of configuration; logical, physical, geometric and parametric are available to define a system. Visionaries can be associated for each function within the system and handled as a single product.

Hierarchical design and block reuse

Circuit and system capture is made easier with the use of hierarchical block, multi-sheet and support circuit and block diagram reuse.

Multi-user product design

Teams can work on designs in parallel using System Planner concurrent design environment within each visionary. This reduces design timescales.

Design Gateway

No Mount

Design Gateway no mount

Visualization of circuit design elements connected to component that are not mounted for design variants.

Busses and connectors connected to non-mounted parts can also be displayed as non-mounted.

Improved schematic visualization and debugging using lowlight mode

Debugging and checking of the circuit design is made easier with the new lowlight display mode. The improved visualization allows users to work more efficiently and locate item(s) quickly. Engineers can focus on a specific object while still being able to see the context of the circuit design.

Copying and Pasting Constraints

Block constraints can now be reused when copying and pasting the block.

Reuse of Topology Templates

Topology template information can now be exported and imported from a file.

SI Analysis

SI analysis can now be executed from the Electrical Editor and Electrical Viewer.

Netlist Output for Simulink

The connection status in a circuit diagram can be converted into a Simulink block diagram.

JTAG ProVision interface for boundary scan analysis is now supported
As an increasing number of designs use boundary scan for testing, support for JTAG ProVision software is now available. Test information created in JTAG ProVision can be displayed on the circuit design, color coding the circuit data as configured. This will help engineers visually identify potential problem areas on the circuit design data, and improve efficiency and quality of the product design.

Support for Floating Windows

Windows in the sheet editor, E-net browser, component browser etc. can now be moved outside of the design editor window.

Graphical Pin Manager (GPM)

Creation and update of Split/Divided symbols in circuit data

Pin assignment changes made in layout or FPGA design environments are automatically updated to the corresponding symbol of the FPGA component, allowing efficient and easy-to-read schematics with split symbols

Component instance information imported from FPGA design environment

Component property information available from the FPGA designers can now be imported into Graphical Pin Manager and can also be reflected into the circuit data. For example the software version can be specified from the FPGA design team and can be reflected via Graphical Pin Manager into the circuit data.

Design Force

Single Board Photo Data Import

Single board photo data

Import single board photo data

RS274D, RS74X and several other photo formats can be read into Design Force to either a specified data or drawing layer. This functionality assists with both modular design and design reuse by allowing reference information from device manufacturers or data from another design to be read into the active design.

IPC-2581 Output

IPC-2581 (revB) data can be output from either Design Force (single board data) or DFM Elements (single board or panel data).

Reuse of Topology Templates

Topology template information can be exported for subsequent reuse on designs with similar topology requirements. Reusing topology information greatly reduces the time and effort required to manage critical design constraints.

Constraint Browser Reporting Improvements

The constraint browser detailed coupling report can display tracks violating differential pair rules as errors. The report also has an option to only display the tracks that violate the differential pair rule. and filter tracks violating the differential pair rule. Furthermore the differences of lengths and the skews on pinpairs belonging to a skew group can be displayed. The pinpairs violating the reference value in a skew group are displayed in red.

Display of From-To for Vias

Display of From-To for Vias

Vias displayed with the layers from-to information

The canvas view settings form in Design Force has a new option for the display of from-to for vias. The from-to can be display for all vias or only for non-through hole vias. This allows for quick verification of via layer spans. When multiple vias have identical coordinates, their from-to values are merged.

Display of Forward Annotation Changes

The results of forward annotation to Design Force are now listed in a dialog and can be cross-probed with the layout. Cross-probing from the design change log to the PCB layout helps increase efficiency when verifying the items (components or nets) that have been changed as a result of the forward annotation process.

Import of Figures from another Board

Figures, such as the board outline, from another board or panel can be read into the active design in Design Force. The imported figure can be added to either a specified data or drawing layer. This functionality assists with both modular design and design reuse by allowing reference information from device manufacturers or data from another design to be read into the active design.

Differential Pair Routing Enhancements

Differential pair routing

Differential pair snap method options

During differential pair routing, the track width and spacing can be interactively toggled to a different differential pair rule stack. Furthermore, when routing into or from a set of differential pair pins, the snap method now supports auto, 45-degree, corner, none, inside, and short-edge modes.

Improved 3D Export Performance

The Design Force functionality to export 3D data has been improved in two areas. The 3D conversion of layer information has been reduced by 86% and the STEP conversion process time has been reduced by 78%. Overall, the processing time for 3D export has been reduced by an average of 43%.

Electrical Editor and Signal Integrity Analysis Enhancements

Topology viewer

Choose the tool type for viewing topology

The tool type for viewing topology (Electrical Viewer or Electrical Editor) may be specified in Design Force application settings. Furthermore, Signal Integrity analysis can be run from either the Electrical Editor or the Electrical Viewer.

Graphical User Interface for CAM Outputs

The Design Force export function now includes a Graphical User Interface (GUI) for the export of photo data and drill data.

DFM Elements

Photo and Drill Output

DFM Elements photo export

Export Photo Data directly from the panel data

Photo and drill data can be output directly from design data or panel data. The requirement in previous releases to first create manufacturing design data (.fpr file) prior to photo and drill output has been removed.

ODB++ Output

ODB++ can be output directly from design data or panel data. The requirement in previous releases to first create manufacturing design data (.fpr file) prior to photo and drill output has been removed.

IDF and DXF Enhancements

IDF data can be imported into manufacturing panel data. DXF data and IDF data can be output from manufacturing panel data.

Design Force ADMZuken’s CR-8000, the industry’s only product-centric design solution, continues to lead the way with next-generation tools capable of creating today’s and tomorrow’s complex product designs. CR-8000 2014 and 2014.1 offer many enhancements to improve product delivery schedules and reduce costly, error-prone steps in the design process.

System Planner, Design Gateway, Design Force, and DFM Center – the core of Zuken’s CR-8000 2D/3D multi-board and IC packaging design solution – contain enhancements that include new placement and routing functionality for both conventional and high-speed designs, 3D mechanical enclosure clearance checking, and interfaces to third party simulation tools.

New CR-8000 Component Editor compatible with CR-5000 Component Manager

CR-8000 offers a new Component Editor that is fully compatible with the existing CR-5000 Component Manager. The user interface for footprint editing is similar to Design Force and DFM Elements, with features that include a tabbed ribbon and dockable/undockable layer and property panels. Support for multiple windows allows for the view and edit of more than one footprint in the same session. Pin information is visible and editable in a table format that supports copy and pasting to Excel for easy creation of a pin table.

Chip-package-board improvements

Chip package co designThe Design Force chip-package-board improvements include:

  • Import of GDS data is supported to allow for the efficient creation of a chip footprint within Design Force.
  • Package design functionality has been improved with the ability to import and export net assignment information using a csv file.
  • Swap nets will swap the pin objects associated with a trace, greatly improving the ability to manage bundles of nets and their connected objects.
  • Nets between routes can be automatically assigned after the fan-in and fan-out operations typically associated with co-design or advanced packaging operations are completed.
  • Spacer components can be generated as pin-less components

ADM improvements to support Board Designer to Design Force transition

Design Force ADMDesign Force no longer runs ADM using the DFM Center check engine, but instead uses the same check engine as Board Designer. As a result the ADM rule manager, the check engine, and the check results are now the same between Board Designer and Design Force. ADM can be executed with a frame select (similar to DRCs), or ADM can be executed in batch mode from the CR-8000 desktop. Execution from the CR-8000 desktop provides an alternative to starting Design Force in order to run manufacturing audits.

CR-8000 2014Zuken’s CR-8000, the industry’s only product-centric design solution, continues to lead the way with next-generation tools capable of creating today’s and tomorrow’s complex product designs. CR-8000 2014 and 2014.1 offer many enhancements to improve product delivery schedules and reduce costly, error-prone steps in the design process.

System Planner, Design Gateway, Design Force, and DFM Center – the core of Zuken’s CR-8000 2D/3D multi-board and IC packaging design solution – contain enhancements that include new placement and routing functionality for both conventional and high-speed designs, 3D mechanical enclosure clearance checking, and interfaces to third party simulation tools.

Improved drawing functionality and linkage to MCAD tools

System Planner improved drawingSystem Planner has improved drawing functionality in both Logical and Physical Visionaries. The Logical Visionary includes additional stencils to assist with the creation of block diagrams. Any image in the clipboard can be pasted into either logical or physical planning stages as a “comment” shape.

Additional improvements include:

  • Properties changed in a circuit that has been exported from System Planner can be reloaded into the source System Planner data. When a Design Gateway schematic that had previously been exported from
  • System Planner is updated, the Design Gateway updates are then automatically reflected in System Planner’s various planning stages.
    IDF data can be imported into System Planner. For example, 3D IDF data can be imported and viewed in the physical planning stage.

Reusable constraints and signal continuity checks

Design Gateway reusable constraintsWhen using Design Gateway’s multi-board functionality, net properties can be checked for consistency between the various board level schematics within the overall system. Users can also probe from the connector of one board in the system to the connector(s) of other boards in the system to quickly and easily confirm connections between the various circuits.

Within Design Gateway’s hierarchical design functionality, a new check for mismatches between the block pin label and the net/bus label is available. This will greatly reduce the chance of accidental connection errors.

Constraint information for each functional block is directly associated with the block circuit, enabling copying and editing of constraints by block. Constraints can be managed at the block level and, more importantly, the constraints associated with reuse circuits are also reusable. This reduces the need to manage all constraints from the top level circuit.

Enhanced placement and routing

Design Force enhanced placement and routingDesign Force has added placement and routing templates to enable designers who work with bus routing or flex circuits to follow either reference routing or the board outline, then save the route as a template for parallel routes within the same design. When placing components support for a new “unplaced” status has been added providing greater flexability when moving and placing parts. For high-speed designs, topology templates can be created based on reference designs that include guidelines for track lengths, widths and spacing – greatly reducing the effort to configure and manage constraints, especially with differential pair routing. When routing a differential pair, Design Force not only displays the length of the entire track, it also displays the length from each source pin along with the length difference. The Pin Pair Route Report supports the highlighting of pin-pairs on the canvas from the Constraint Browser. Support for bent differential/bundle routes allows for faster interactive routing without the need to digitize precise positions for each corner.

Signal Integrity, Power Integrity and EMI Analysis enhancements

CR-8000 Analysis Result ViewerCR-8000 simulation and analysis tools support eye pattern analysis, enabling the verification of results using an eye pattern diagram. During waveform analysis of DDR clock or fast differential signals, verification can be carried out using colored eye patterns and superimposed bits. Support for parameter sweep analysis of transmission lines and passive component constants has also been added. This provides increased operational efficiency in reusing sweep condition settings and ease in verifying sweep results for multiple conditions. Users can check cross-sections of transmission lines in the electrical viewer/editor, taking into account the etch factor. This makes verification more intuitive and considers trapezoidal cross sections.

3D mechanical enclosure clearance verification

Multi-board product design – a unique feature of CR-8000 permitting the coordinated design of multiple boards in one product – enables checking of 3D clearance between boards directly within the PCB design environment. It also reports and cross-probes to any clearance violations between objects including board outlines, components, nets and mechanical data.

Interface with third-party simulation tools

Design Force interface with simulation toolsDesign Force 2014 has increased support for a number of third party simulation and analysis tools. Users may:

  • Import conductor figures generated in AWR Microwave Office into Design Force using the new Import IFF function.
  • Import data on the optimization of decoupling capacitors from ANSYS PI Advisor into Design Force using the new Import PI Advisor function.
  • Exchange bidirectional information with Agilent ADS using the new ADS Board Link file format.