Zuken will be hosting at the Embassy Suites Dallas-Frisco/Hotel, Convention Center & Spa room# 205.
Conference Mission: To promote the exchange of ideas and experience for the benefit of those people concerned with transmission and substation design and development.
Access to the 2018 Annual TSDOS Post-Conference Report here.
Access to the 2018 Technical papers here.
The Largest Conference and Exhibition for Printed Circuit Board Design, Fabrication, and Assembly in the Silicon Valley
For 28 years PCB West has trained designers, engineers, fabricators and, lately, assemblers on making printed circuit boards for every product or use imaginable. The September 2018 event attracted nearly 2,000 designers and engineers and more than 100 exhibitors for the three-day technical conference and one-day sold-out exhibition. From high-reliability military/aerospace to cutting-edge IoT and wearables, there’s something for everyone involved in the electronics supply chain. This is one show you cannot afford to miss.
We will be exhibiting Tuesday, September 10 and our booth number is #500.
Need a caffeine fix? Visit the team in booth #500 between 10 am and 2 pm on September 10th for a free cup on us!
Title: System I/O Optimization with SoC, SiP, PCB Co-Design
Presenter: Lance Wang
Abstract: The increasing complexity of system on chips (SoCs) combined with a new generation of designs that combine multiple chips in a single package is creating new challenges in the design of packages, printed circuit boards (PCBs) and integrated circuits (ICs). The process typically involves three independent design processes – chip, package, and PCB – carried out with point tools whose interface requires time-consuming manual processes that are error-prone and limit the potential for reuse. This challenge is being addressed by a new integrated 3D chip/package/board co-design environment that makes it possible to holistically optimize the package, board and IC design to a greater degree than was possible in the past by considering the system-level impact of each design decision. The new co-design approach enables designers to optimize routability via pin assignment and I/O placement to achieve minimum layer counts between chip, package, and board. The end result is higher performance.
Each year, IWLPC sets the stage in the heart of Silicon Valley, providing attendees with the opportunity to network and attend presentations by industry experts. IWLPC is a highly regarded technical conference that covers leading-edge advancements in wafer-level packaging.
With this year’s theme, “Driving an Interconnected World,” the program tracks comprised WLP/FOWLP, 2.5D/3D, and Advanced Manufacturing and Test.