Upcoming Events

Oct
1
Tue
IMAPS 2019
Oct 1 – Oct 3 all-day

Title: System I/O Optimization with SoC, SiP, PCB Co-Design

Presenter: Lance Wang

Abstract: The increasing complexity of system on chips (SoCs) combined with a new generation of designs that combine multiple chips in a single package is creating new challenges in the design of packages, printed circuit boards (PCBs) and integrated circuits (ICs). The process typically involves three independent design processes – chip, package, and PCB – carried out with point tools whose interface requires time-consuming manual processes that are error-prone and limit the potential for reuse. This challenge is being addressed by a new integrated 3D chip/package/board co-design environment that makes it possible to holistically optimize the package, board and IC design to a greater degree than was possible in the past by considering the system-level impact of each design decision. The new co-design approach enables designers to optimize routability via pin assignment and I/O placement to achieve minimum layer counts between chip, package, and board. The end result is higher performance.

 

Oct
22
Tue
IWLPC 2019
Oct 22 – Oct 24 all-day

Each year, IWLPC sets the stage in the heart of Silicon Valley, providing attendees with the opportunity to network and attend presentations by industry experts. IWLPC is a highly regarded technical conference that covers leading-edge advancements in wafer-level packaging.

With this year’s theme, “Driving an Interconnected World,” the program tracks comprised WLP/FOWLP, 2.5D/3D, and Advanced Manufacturing and Test.

Come visit us at table #61!

Oct
23
Wed
Komax Customer Appreciation Event
Oct 23 @ 8:30 am – Oct 24 @ 4:00 pm

Please join us for Customer Appreciation Days on October 23rd and 24th!

Experience hands-on demonstrations and informational seminars on the very latest in:

Automated Wire Processing Equipment and Processes

Application Tooling

Design Software and Development Tools

and get a sneak peek at what’s next for 2020!

Wednesday, October 23rd, 2019 Thursday, October 24th, 2019 8:30am – 4:00pm 1100 East Corporate Grove Drive, Buffalo Grove, IL 60089-4507

October 2019 Meeting, Silicon Valley Chapter – IPC Designers Council
Oct 23 @ 2:30 pm – 4:30 pm

Topic: Best Practices for RF and Mixed Technology PCB Design    

The successful design of modern, complex mixed-technology PCBs is an ever-evolving task. As technologies change, techniques employed by designers must evolve accordingly. The aim of this session is to show how designs can be done as correctly as possible on the first attempt. Doing so has been repeatedly found to yield good results from simulations and testing, with minimal design modification required. Regards of the mathematics and simulations that may be employed, strict adherence to best practices is most likely to make the board “just work”.

Speaker: Scott Nance, Director of PCB Layout, Optimum Design Associates

Scott is a veteran designer with over 30 years of experience and a breadth of knowledge in all aspects of PCB design. Scott came to Optimum in 2005, and has created multiple boards utilized for NASA and the military. Scott has also used his talents as a designer to create PCBs for audio, aviation, and consumer electronics industries. In 2013, Scott represented Optimum as a featured speaker at PCB West 2013, one of the industry’s largest tradeshows and authored the article, “A Whole Lot of Switchin Goin On”..

Agenda:                                                         

Lunch served               11:30 – 11:40

Misc. Business             11:40 – 11:50

Host’s Highlights          11:50 – 12:00

Sponsor’s Spotlight      12:00 – 12:15

Presentation                12:15 – 1:00

Q & A discussion         1:00 – 1:15

Wrap-Up                      1:15 – 1:30