Avoiding Poor FPGA I/O Assignments for PCB Design
FPGA I/O assignments can determine the difference between an optimally performing design and an unroutable PCB. Using the latest devices from Xilinx, Altera, Lattice and Microsemi, this webinar will demonstrate best practices and techniques on how to select your FPGA I/O assignments for optimal PCB and design performance.
The webinar will explore various points in the design flow where co-design of the FPGA and board layout can take place; this includes library part creation, schematic entry, I/O optimization and pin assignment management during board layout. See how a FPGA / PCB co-design process can improve overall design quality in less time.
What you’ll learn:
- The critical steps is an effective FPGA / PCB co-design process
- How to optimize your FPGA pin assignments for improved PCB routing
- How component creation can impact your design
- How to share FPGA pin assignments optimized for PCB with FPGA vendor tools
Who should attend:
- Engineering managers
- Hardware engineers
- FPGA engineers
- PCB designers